Aopen Digital Engine DEX4501 Watch Dog Timer Driver for Mac

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Aopen Digital Engine DEX4501 Watch Dog Timer Driver

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Aopen Digital Engine DEX4501 Watch Dog Timer Driver

Many people are happy to concentrate on getting the latest and greatest processor, a GeForce 5 graphics card review coming soon.

Memory - if it is considered at all - is thought of in terms of quantity rather than quality. Or is it.

In fact, poor quality RAM is probably the single biggest cause of unstable systems we see reported on the forums and newsgroups. It is almost guaranteed that a user suffering frequent system crashes will have generic PC SDRAM on their list of system components somewhere.

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Cheap RAM, along with small power supplies, are the two greatest false economies a system constructor can make. Good quality RAM, although more expensive, buys both stability and performance.

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They are generally poorly designed modules with dubious stability. Would you buy a processor or motherboard from an unknown company.

To start with, we need to consider a little memory theory to understand the choices available to us. A unique feature of these chipsets is the asynchronous memory bus, which means that the memory bus can run at a different speed to the front side bus FSB. The earlier KX chipset also supports a 66MHz memory bus.

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Can this be used on a MHz memory bus and is it worth the extra money. Memory designed to run at MHz is called PC and conforms to a stringent standard defined by Intel.


An important consideration for SDRAM is the rate at which it can transfer data to and from the processor. This is illustrated in the figure below.

As the memory bus is bits or 8 bytes wide, the memory speed directly determines the theoretical peak rate at which data can be passed to and from the Northbridge. This means that the FSB supports a peak data rate of 1.

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VIA KT block diagram from VIA s website Memory Timings In practice, memory benchmarks show that is difficult to achieve an average data throughput that is Aopen Digital Engine DEX4501 Watch Dog Timer half the theoretical peak transfer rate on the memory bus. In simple terms, however, the memory cannot simply instantly provide data with each clock cycle. There is an initial overhead or latency associated with a request to read or write data from a given memory address, followed by the data appearing on each clock cycle.

It Aopen Digital Engine DEX4501 Watch Dog Timer hard to describe these overheads without repeating the detailed descriptions of SDRAM operations in the references above, but if for simplicity we simply regard the memory as a table with rows and columns, then the principle delays are: CAS latency: PC x-y-z. Although measured in clock cycles, the underlying reasons for these delays are due to the actual time taken for signals to settle within the SDRAM chip.

The timings are therefore specified for a given memory speed, and will change with bus frequency. It all depends on the quality of the RAM. To summarise all this timing technobabble, the point to realise is that the performance of the memory depends on not just the MHz but also on how efficiently the RAM uses each clock cycle. To make matters more confusing, suppliers often abbreviate these timings to just the first number - Aopen Digital Engine DEX4501 Watch Dog Timer CAS latency, eg.

It is up to you, as the buyer, to do your research.

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If a supplier doesn t provide this information, choose one who does. What does this all mean to me. You want to know whether your computer will be more stable or faster, if you invest in some quality RAM. How does the CAS latency affect things. How far can you overclock the RAM and how does this help. This is what this article attempts to address.

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Memory Under Test: For those of you who like looking at pictures, here it is: What more is there to say.

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